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315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
MAX1471
ADATA
DATA
SLICER
MAXIMUM PEAK
DETECTOR
PDMAXA
MINIMUM PEAK
DETECTOR
PDMINA
FDATA
PDMAXF
C
R
R
PDMINF
C
Figure 5. Generating Data-Slicer Threshold Using the Peak Detectors
MINIMUM PEAK
DETECTOR
PDMINA
PDMINF
BASEBAND
FILTER
TRK_EN = 1
MAXIMUM PEAK
DETECTOR
PDMAXA
PDMAXF
TO SLICER
INPUT
MAX1471
Figure 6. Peak-Detector Track Enable
TRK_EN = 1
Power-Supply Connections
The MAX1471 can be powered from a 2.4V to 3.6V
supply or a 4.5V to 5.5V supply. The device has an on-
chip linear regulator that reduces the 5V supply to 3V
needed to operate the chip.
To operate the MAX1471 from a 3V supply, connect
DVDD, AVDD, and HVIN to the 3V supply. When using
a 5V supply, connect the supply to HVIN only and con-
nect AVDD and DVDD together. In both cases, bypass
DVDD and HVIN with a 0.01μF capacitor and AVDD
with a 0.1μF capacitor. Place all bypass capacitors as
close as possible to the respective supply pin.
Control Interface Considerations
When operating the MAX1471 with a +4.5V to +5.5V
supply voltage, the CS , DIO, and SCLK pins can be dri-
ven by a microcontroller with either 3V or 5V interface
logic levels. When operating the MAX1471 with a +2.4V
to +3.6V supply, only 3V logic from the microcontroller
is allowed.
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